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LATTICE

萊迪思半導(dǎo)體公司成立于 1983 年，總部設(shè)在美國俄勒岡州波特蘭市，是智能連接解決方案的全球領(lǐng)導(dǎo)者。 他們提供市場領(lǐng)先的知識產(chǎn)權(quán)和低功耗、小尺寸器件，能夠讓 8,000 多個全球客戶快速實(shí)現(xiàn)與眾不同的創(chuàng)新的經(jīng)濟(jì)、節(jié)能產(chǎn)品。 該公司在廣泛的終端市場上四處出擊，產(chǎn)品覆蓋從消費(fèi)電子到工業(yè)設(shè)備、通信基礎(chǔ)設(shè)施和許可。
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為您找到相關(guān)結(jié)果 16371 條 1414 /1638
ISPLSI2032-135LJI
型號：
ISPLSI2032-135LJI
品牌：
LATTICE
產(chǎn)品分類：
集成電路
描述：
Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. Features ? ENHANCEMENTS ?? — ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging ?? — ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS? Technology ? HIGH DENSITY PROGRAMMABLE LOGIC ?? — 1000 PLD Gates ?? — 32 I/O Pins, Two Dedicated Inputs ?? — 32 Registers ?? — High Speed Global Interconnect ?? — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. ?? — Small Logic Block Size for Random Logic ? HIGH PERFORMANCE E2CMOS? TECHNOLOGY ?? — fmax = 180 MHz Maximum Operating Frequency ?? — tpd = 5.0 ns Propagation Delay ?? — TTL Compatible Inputs and Outputs ?? — Electrically Erasable and Reprogrammable ?? — Non-Volatile ?? — 100% Tested at Time of Manufacture ?? — Unused Product Term Shutdown Saves Power ? IN-SYSTEM PROGRAMMABLE ?? — In-System Programmable (ISP?) 5V Only ?? — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality ?? — Reprogram Soldered Devices for Faster Prototyp ? OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBIL OF FIELD PROGRAMMABLE GATE ARRAYS ?? — Complete Programmable Device Can Combine G Logic and Structured Designs ?? — Enhanced Pin Locking Capability ?? — Three Dedicated Clock Input Pins ?? — Synchronous and Asynchronous Clocks ?? — Programmable Output Slew Rate Control to Minimize Switching Noise ?? — Flexible Pin Placement ?? — Optimized Global Routing Pool Provides Global Interconnectivity
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