ISPLSI2032-135LT48I
型號: ISPLSI2032-135LT48I
類別: 集成電路
描述: Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. Features ? ENHANCEMENTS ?? — ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging ?? — ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS? Technology ? HIGH DENSITY PROGRAMMABLE LOGIC ?? — 1000 PLD Gates ?? — 32 I/O Pins, Two Dedicated Inputs ?? — 32 Registers ?? — High Speed Global Interconnect ?? — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. ?? — Small Logic Block Size for Random Logic ? HIGH PERFORMANCE E2CMOS? TECHNOLOGY ?? — fmax = 180 MHz Maximum Operating Frequency ?? — tpd = 5.0 ns Propagation Delay ?? — TTL Compatible Inputs and Outputs ?? — Electrically Erasable and Reprogrammable ?? — Non-Volatile ?? — 100% Tested at Time of Manufacture ?? — Unused Product Term Shutdown Saves Power ? IN-SYSTEM PROGRAMMABLE ?? — In-System Programmable (ISP?) 5V Only ?? — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality ?? — Reprogram Soldered Devices for Faster Prototyp ? OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBIL OF FIELD PROGRAMMABLE GATE ARRAYS ?? — Complete Programmable Device Can Combine G Logic and Structured Designs ?? — Enhanced Pin Locking Capability ?? — Three Dedicated Clock Input Pins ?? — Synchronous and Asynchronous Clocks ?? — Programmable Output Slew Rate Control to Minimize Switching Noise ?? — Flexible Pin Placement ?? — Optimized Global Routing Pool Provides Global Interconnectivity
品牌官網(wǎng): www.latticesemi.com
- 賣盤信息
- 常見問題
- 參數(shù)
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平臺購物流程是怎樣的?
平臺商品來源有保障嗎?
平臺上展示的商品數(shù)量、價格及相關(guān)信息準確嗎?
平臺支持BOM詢價嗎?
平臺下單后什么時候能發(fā)貨?多久能到?
拍明芯城的訂單如何跟蹤?
拍明芯城的訂單可以提供合同嗎?
拍明芯城的發(fā)票如何開具?
參數(shù) | 數(shù)值 |
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Series
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ispLSI2000
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Number of macrocells
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32
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Number of gates
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1000
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Power-supply voltage
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5V
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Package
|
TQFP
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Lifecyle
|
Obsolete
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Description
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CPLD ispLSI? 2000 Family 1K Gates 32 Macro Cells 137MHz 0.35um Technology 5V 48-Pin TQFP
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Taxonomy
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Programmable Devices > Programmable Logic Devices > Complex Programmable Logic Devices - CPLDs
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Country Of Origins
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Malaysia, Indonesia, Republic of Korea
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Introduction Date
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2002-02-11 00
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EU RoHS
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No
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HTSUSA
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8542390001
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EU RoHS Version
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2011/65/EU, 2015/863
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Part Number Code
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View Code
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Supplier Cage Code
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66675
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