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型號： Q67120-C2200

類別： 集成電路

描述： Introduction The C167CS-xC derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM. C167CS-xC ? High Performance 16-bit CPU with 4-Stage Pipeline ?? – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock ?? – 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division (32/16 bit) ?? – Enhanced Boolean Bit Manipulation Facilities ?? – Additional Instructions to Support HLL and Operating Systems ?? – Register-Based Design with Multiple Variable Register Banks ?? – Single-Cycle Context Switching Support ?? – 16 MBytes Total Linear Address Space for Code and Data ?? – 1024 Bytes On-Chip Special Function Register Area ? 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns ? 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) ? Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input ? On-Chip Memory Modules ?? – 3 KBytes On-Chip Internal RAM (IRAM) ?? – 8 KBytes On-Chip Extension RAM (XRAM) ?? – 32 KBytes On-Chip Program Mask ROM ? On-Chip Peripheral Modules ?? – 24-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 μs ?? – Two 16-Channel Capture/Compare Units ?? – 4-Channel PWM Unit ?? – Two Multi-Functional General Purpose Timer Units with 5 Timers ?? – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) ?? – Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 × 15 Message Objects (Full CAN/Basic CAN), can work on one bus with 30 objects ?? – On-Chip Real Time Clock ? Up to 16 MBytes External Address Space for Code and Data ?? – Programmable External Bus Characteristics for Different Address Ranges ?? – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width ?? – Five Programmable Chip-Select Signals ?? – Hold- and Hold-Acknowledge Bus Arbitration Support ? Idle, Sleep, and Power Down Modes with Flexible Power Management ? Programmable Watchdog Timer and Oscillator Watchdog ? Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis ? Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards ? On-Chip Bootstrap Loader

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