5962-9558701MXC(E2VLATTICE)
型號(hào): 5962-9558701MXC(E2VLATTICE)
類(lèi)別: 現(xiàn)場(chǎng)可編程邏輯陣列
描述: CPLD ispLSI? 1000 Family 8K Gates 192 Macro Cells 50.3MHz 5V 133-Pin CPGA
品牌官網(wǎng): www.teledyne-e2v.com
- 賣(mài)盤(pán)信息
- 常見(jiàn)問(wèn)題
- 參數(shù)
-
平臺(tái)購(gòu)物流程是怎樣的?
平臺(tái)商品來(lái)源有保障嗎?
平臺(tái)上展示的商品數(shù)量、價(jià)格及相關(guān)信息準(zhǔn)確嗎?
平臺(tái)支持BOM詢價(jià)嗎?
平臺(tái)下單后什么時(shí)候能發(fā)貨?多久能到?
拍明芯城的訂單如何跟蹤?
拍明芯城的訂單可以提供合同嗎?
拍明芯城的發(fā)票如何開(kāi)具?
參數(shù) | 數(shù)值 |
---|---|
EURoHS
|
SupplierUnconfirmed
|
PartStatus
|
Active
|
FamilyName
|
ispLSI?1000
|
ProgramMemoryType
|
ROMLess
|
NumberofLogicBlocks/Elements
|
48
|
NumberofGlobalClocks
|
4
|
NumberofMacroCells
|
192
|
DeviceSystemGates
|
8000
|
DataGate
|
No
|
MaximumNumberofUserI/Os
|
96
|
NumberofFlipFlops
|
288
|
In-SystemProgrammability
|
Yes
|
Programmability
|
Yes
|
ReprogrammabilitySupport
|
Yes
|
MaximumInternalFrequency(MHz)
|
58.8
|
MaximumClocktoOutputDelay(ns)
|
16
|
MaximumPropagationDelayTime(ns...
|
26
|
SpeedGrade
|
50
|
IndividualOutputEnableControl
|
Yes
|
MinimumOperatingSupplyVoltage(...
|
4.5
|
MaximumOperatingSupplyVoltage(...
|
5.5
|
TypicalOperatingSupplyVoltage(...
|
5
|
MaximumOperatingCurrent(mA)
|
260
|
MinimumOperatingTemperature(°C...
|
-55
|
MaximumOperatingTemperature(°C...
|
125
|
SupplierTemperatureGrade
|
Military
|
PinCount
|
133
|
SupplierPackage
|
CPGA
|
StandardPackageName
|
PGA
|
Tradename
|
ispLSI
|
Mounting
|
ThroughHole
|
PCBchanged
|
133
|